FPGA作为从机与STM32用SPI的方式进行通信，结果显示在OLED上

本人首先用两片STM32F1以软件的方式进行SPI通信，一主一从以便了解SPI协议，通信测试成功（实际中一般用硬件spi）。然后用STM32F1主机与FPGA进行通信，根据从机STM32F1从机的接收代码改为Verilog，并且将SPI接收到的数据显示在0.96寸OLED(FPGA驱动OLED也是SPI方式，只是FPGA作为主机了)上。

#include “can.h“
#include “usart.h“


//CAN初始化
//tsjw:重新同步跳跃时间单元.范围:CAN_SJW_1tq~ CAN_SJW_4tq
//tbs2:时间段2的时间单元.   范围:CAN_BS2_1tq~CAN_BS2_8tq;
//tbs1:时间段1的时间单元.   范围:CAN_BS1_1tq ~CAN_BS1_16tq
//brp :波特率分频器.范围:1~1024;  tq=（brp）*tpclk1
//波特率=Fpclk1/（（tbs1+tbs2+1）*brp）;
//mode:CAN_Mode_Normal普通模式;CAN_Mode_LoopBack回环模式;
//Fpclk1的时钟在初始化的时候设置为36M如果设置CAN_Mode_Init（CAN_SJW_1tqCAN_BS2_8tqCAN_BS1_9tq4CAN_Mode_LoopBack）;
//则波特率为:36M/（（8+9+1）*4）=500Kbps
//返回值:0初始化OK;
//    其他初始化失败;
u8 CAN_Mode_Init（u8 tsjwu8 tbs2u8 tbs1u16 brpu8 mode）	 
{
	GPIO_InitTypeDef  GPIO_InitStructure;
	CAN_InitTypeDef	 CAN_InitStructure;
	CAN_FilterInitTypeDef CAN_FilterInitStructure;

#if CAN_RX0_INT_ENABLE 
	NVIC_InitTypeDef  		NVIC_InitStructure;
#endif

	RCC_APB1PeriphClockCmd（RCC_APB1Periph_CAN1 ENABLE）; //打开CAN1时钟
	RCC_APB2PeriphClockCmd（RCC_APB2Periph_GPIOA ENABLE）;   //PA端口时钟打开
	
	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;		//PA11	   
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 	 //上拉输入模式
	GPIO_Init（GPIOA &GPIO_InitStructure）;	

	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;		//PA12	   
	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 	 //复用推挽输出
	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	 //IO口速度为50MHz
	GPIO_Init（GPIOA &GPIO_InitStructure）;

	CAN_InitStructure.CAN_Prescaler=brp;  //分频系数
	CAN_InitStructure.CAN_Mode=mode;  //CAN工作模式  环回模式
	CAN_InitStructure.CAN_SJW=tsjw; //重新同步跳跃宽度 1 个时间单位
	CAN_InitStructure.CAN_BS1=tbs1; //时间段 1 为 8 个时间单位
	CAN_InitStructure.CAN_BS2=tbs2; //时间段 2 为 7 个时间单位
	CAN_InitStructure.CAN_TTCM=DISABLE; //非时间触发通信模式
	CAN_InitStructure.CAN_ABOM=DISABLE; //失能自动离线管理
	CAN_InitStructure.CAN_AWUM=DISABLE; //失能自动唤醒模式
	CAN_InitStructure.CAN_NART=ENABLE; //使能非自动重传输模式
	CAN_InitStructure.CAN_RFLM=DISABLE; //失能接收 FIFO 锁定模式
	CAN_InitStructure.CAN_TXFP=DISABLE; //失能发送 FIFO 优先级
	CAN_Init（CAN1&CAN_InitStructure）;

	CAN_FilterInitStructure.CAN_FilterNumber=0;	//过滤器0
	CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask; 	//屏蔽位模式
	CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit; 	//32位宽 
	CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;	//32位ID
	CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
	CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;//32位MASK
	CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
	CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_Filter_FIFO0;//过滤器0关联到FIFO0
	CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;//激活过滤器0
	CAN_FilterInit（&CAN_FilterInitStructure）;			//滤波器初始化

#if CAN_RX0_INT_ENABLE 
	CAN_ITConfig（CAN1CAN_IT_FMP0ENABLE）;				//FIFO0消息挂号中断允许.		    

	NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;     // 主优先级为1
	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;            // 次优先级为0
	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
	NVIC_Init（&NVIC_InitStructure）;
#endif
	return 0;
}

#if CAN_RX0_INT_ENABLE	//使能RX0中断
//中断服务函数			    
void USB_LP_

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----
     目录           0  2018-11-30 21:56  OLED_SPI_STM32_FPGA\
     目录           0  2018-11-10 18:23  OLED_SPI_STM32_FPGA\OLED_CSDN\
     目录           0  2018-11-30 21:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\
     文件         356  2018-11-13 00:14  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\MY_PLL.ppf
     文件         360  2018-11-13 00:14  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\MY_PLL.qip
     文件       14616  2018-11-13 00:14  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\MY_PLL.v
     文件       10826  2018-11-13 00:14  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\MY_PLL_bb.v
     文件         932  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL.cmp
     文件         859  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL.inc
     文件         413  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL.ppf
     文件         518  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL.qip
     文件       15455  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL.vhd
     文件         253  2018-11-30 21:46  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLLJ_PLLSPE_INFO.txt
     文件         360  2018-08-12 18:53  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL_1M_10K.ppf
     文件         372  2018-08-12 18:53  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL_1M_10K.qip
     文件       10866  2018-08-12 18:53  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL_1M_10K_bb.v
     文件         101  2018-11-12 20:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\PLL_inst.vhd
     文件         968  2018-08-08 14:12  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\ROM.cmp
     文件         359  2018-08-08 14:12  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\ROM.qip
     文件        6287  2018-08-08 14:12  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\ROM.vhd
     文件          99  2018-08-08 14:12  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\ROM_inst.vhd
     文件         371  2017-10-19 10:08  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\Tcl_script1.tcl
     文件         371  2017-10-17 13:45  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\Tcl_script1.tcl.bak
     目录           0  2018-11-30 18:54  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\__Previews\
     文件       32943  2018-11-30 18:54  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\__Previews\fq_get.vPreview
     目录           0  2018-11-30 21:52  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\
     文件         201  2017-10-22 10:31  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\.cmp.kpt
     文件        3946  2018-08-12 19:38  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\MY_PLL_altpll.v
     文件        3942  2018-11-13 00:10  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\MY_PLL_altpll1.v
     文件        4102  2018-11-12 20:53  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\PLL_altpll.v
     文件        1733  2018-08-06 10:36  OLED_SPI_STM32_FPGA\OLED_CSDN\OLED\db\add_sub_7pc.tdf
............此处省略943个文件信息