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VGA 显示colour bar实验
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/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_adc.c
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file provides all the ADC firmware functions.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include “stm32f10x_adc.h“
#include “stm32f10x_rcc.h“
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ADC ADON mask */
#define CR2_ADON_Set ((u32)0x00000001)
#define CR2_ADON_Reset ((u32)0xFFFFFFFE)
/* ADC DMA mask */
#define CR2_DMA_Set ((u16)0x0100)
#define CR2_DMA_Reset ((u16)0xFEFF)
/* ADC RSTCAL mask */
#define CR2_RSTCAL_Set ((u16)0x0008)
/* ADC CAL mask */
#define CR2_CAL_Set ((u16)0x0004)
/* ADC SWSTRT mask */
#define CR2_SWSTRT_Set ((u32)0x00400000)
/* ADC DISCNUM mask */
#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)
/* ADC DISCEN mask */
#define CR1_DISCEN_Set ((u32)0x00000800)
#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)
/* ADC EXTTRIG mask */
#define CR2_EXTTRIG_Set ((u32)0x00100000)
#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)
/* ADC Software start mask */
#define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000)
#define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF)
/* ADC JAUTO mask */
#define CR1_JAUTO_Set ((u32)0x00000400)
#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)
/* ADC JDISCEN mask */
#define CR1_JDISCEN_Set ((u32)0x00001000)
#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)
/* ADC JEXTSEL mask */
#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)
/* ADC JEXTTRIG mask */
#define CR2_JEXTTRIG_Set ((u32)0x00008000)
#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)
/* ADC JSWSTRT mask */
#define CR2_JSWSTRT_Set ((u32)0x00200000)
/* ADC injected software start mask */
#define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000)
#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF)
/* ADC AWDCH mask */
#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)
/* ADC
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