xilinx DDR3接口代码VerilogHDLC

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     目录           0  2019-03-06 16:50  mig_7series_0_example\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\constrs_1\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\constrs_1\imports\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\constrs_1\imports\par\
     文件        2801  2014-10-10 17:45  mig_7series_0_example\mig_7series_0_example.srcs\constrs_1\imports\par\example_top.xdc
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\imports\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\imports\rtl\
     文件       63761  2014-09-25 20:37  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\imports\rtl\example_top.v
     文件       12912  2014-09-24 02:10  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\imports\rtl\led_display_driver.v
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\
     目录           0  2019-03-06 16:50  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\
     文件       14918  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_allx_typeA.v
     文件       14982  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_allx_typeA_nodelay.v
     文件       12215  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_all_typeA.v
     文件        7137  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_all_typeA_slice.v
     文件        4713  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_async_edge_xfer.v
     文件        5795  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_async_xfer.v
     文件        4583  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_bscan.v
     文件        4109  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_buf.v
     文件        4369  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_cfglut4.v
     文件        4823  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_cfglut5.v
     文件        5276  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_cfglut6.v
     文件        6075  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_cfglut7.v
     文件        7590  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_cfglut8.v
     文件       12065  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_generic_memrd.v
     文件        4369  2014-10-10 15:05  mig_7series_0_example\mig_7series_0_example.srcs\sources_1\ip\vio_0\ltlib_v1_0\hdl\verilog\ltlib_v1_0_generic_mux.v
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