一种异步fifo实现（论文+hdl实现）

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

 属性            大小     日期    时间   名称
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     文件    1239930  2013-01-12 12:19  wave.bmp

     文件       1436  2013-01-12 12:21  tb.do

     文件       1300  2013-01-12 12:19  wave.do

     文件      73728  2013-01-12 12:22  vsim.wlf

     文件       1233  2013-01-11 12:44  fifo1.xml

     文件       1142  2013-01-12 12:05  src\wptr_full.v

     文件       1151  2013-01-12 11:01  src\rptr_empty.v

     文件        345  2013-01-12 12:06  src\sync_w2r.v

     文件        349  2013-01-12 12:06  src\sync_r2w.v

     文件        924  2013-01-12 12:08  src\fifo1_tb.v

     文件        671  2013-01-11 20:32  src\fifomem.v

     文件       1925  2013-01-12 10:37  src\fifo1.v

     文件       2002  2013-01-12 12:22  work\_info

     文件         26  2013-01-12 12:22  work\_vmake

     文件        695  2013-01-12 12:22  work\fifomem\_primary.vhd

     文件      10728  2013-01-12 12:22  work\fifomem\verilog.psm

     文件        306  2013-01-12 12:22  work\fifomem\verilog.prw

     文件        601  2013-01-12 12:22  work\fifomem\_primary.dbs

     文件        490  2013-01-12 12:22  work\fifomem\_primary.dat

     文件        449  2013-01-12 12:22  work\sync_r2w\_primary.vhd

     文件       5760  2013-01-12 12:22  work\sync_r2w\verilog.psm

     文件        251  2013-01-12 12:22  work\sync_r2w\verilog.prw

     文件        341  2013-01-12 12:22  work\sync_r2w\_primary.dbs

     文件        362  2013-01-12 12:22  work\sync_r2w\_primary.dat

     文件        449  2013-01-12 12:22  work\sync_w2r\_primary.vhd

     文件       5760  2013-01-12 12:22  work\sync_w2r\verilog.psm

     文件        251  2013-01-12 12:22  work\sync_w2r\verilog.prw

     文件        341  2013-01-12 12:22  work\sync_w2r\_primary.dbs

     文件        362  2013-01-12 12:22  work\sync_w2r\_primary.dat

     文件        589  2013-01-12 12:22  work\rptr_empty\_primary.vhd

............此处省略33个文件信息