基于ISE14.7中的RAM模块IP核，采用Verilog，全面了解RAM工作原理

1,实现双口RAM，完全掌握调用IP核的流程; 2,深入了解RAM，模拟1450字节数据，然后写入RAM，完成测试； 3,完成RAM读写测试，数据“顺序”输出。

/**********************************************************************/
/*   ____  ____                                                       */
/*  /   /\/   /                                                       */
/* /___/  \  /                                                        */
/* \   \   \/                                                       */
/*  \   \        Copyright （c） 2003-2009 Xilinx Inc.                */
/*  /   /          All Right Reserved.                                 */
/* /---/   /\                                                         */
/* \   \  /  \                                                      */
/*  \___\/\___\                                                    */
/***********************************************************************/

/* This file is designed for use with ISim build 0x7708f090 */

#define XSI_HIDE_SYMBOL_SPEC true
#include “xsi.h“
#include 
#ifdef __GNUC__
#include 
#else
#include 
#define alloca _alloca
#endif
static unsigned int ng0[] = {0U 0U};



static void Cont_28_0（char *t0）
{
    char *t1;
    char *t2;
    char *t3;
    char *t4;
    char *t5;
    char *t6;
    char *t7;
    unsigned int t8;
    unsigned int t9;
    char *t10;
    unsigned int t11;
    unsigned int t12;
    char *t13;
    unsigned int t14;
    unsigned int t15;

LAB0:    t1 = （t0 + 2344U）;
    t2 = *（（char **）t1）;
    if （t2 == 0）
        goto LAB2;

LAB3:    goto *t2;

LAB2:    t2 = （（char*）（（ng0）））;
    t3 = （t0 + 2728）;
    t4 = （t3 + 56U）;
    t5 = *（（char **）t4）;
    t6 = （t5 + 56U）;
    t7 = *（（char **）t6）;
    memset（t7 0 8）;
    t8 = 1U;
    t9 = t8;
    t10 = （t2 + 4）;
    t11 = *（（unsigned int *）t2）;
    t8 = （t8 & t11）;
    t12 = *（（unsigned int *）t10）;
    t9 = （t9 & t12）;
    t13 = （t7 + 4）;
    t14 = *（（unsigned int *）t7）;
    *（（unsigned int *）t7） = （t14 | t8）;
    t15 = *（（unsigned int *）t13）;
    *（（unsigned int *）t13） = （t15 | t9）;
    xsi_driver_vfirst_trans（t3 0 0）;

LAB1:    return;
}


extern void simprims_ver_m_00000000000126354981_0818475687_init（）
{
	static char *pe[] = {（void *）Cont_28_0};
	xsi_register_didat（“simprims_ver_m_00000000000126354981_0818475687“ “isim/testfor_datagen_isim_translate.exe.sim/simprims_ver/m_00000000000126354981_0818475687.didat“）;
	xsi_register_executes（pe）;
}

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----

     文件        973  2018-10-09 19:55  RAM_Test\DataBuffer.bld

     文件       1074  2018-10-09 20:00  RAM_Test\DataBuffer.cmd_log

     文件          6  2018-10-09 19:54  RAM_Test\DataBuffer.lso

     文件      18063  2018-10-09 19:54  RAM_Test\DataBuffer.ngc

     文件      28184  2018-10-09 19:55  RAM_Test\DataBuffer.ngd

     文件      12172  2018-10-09 19:54  RAM_Test\DataBuffer.ngr

     文件         29  2018-10-09 19:54  RAM_Test\DataBuffer.prj

     文件          0  2018-10-09 19:55  RAM_Test\DataBuffer.stx

     文件      15147  2018-10-09 19:54  RAM_Test\DataBuffer.syr

     文件        206  2018-10-09 20:00  RAM_Test\DataBuffer.tfi

     文件       1874  2018-10-10 15:12  RAM_Test\DataBuffer.v

     文件       1102  2018-10-09 19:54  RAM_Test\DataBuffer.xst

     文件      12962  2018-10-09 19:54  RAM_Test\DataBuffer_xst.xrpt

     文件       1869  2018-10-10 15:10  RAM_Test\fuse.log

     文件        367  2018-10-10 15:10  RAM_Test\fuse.xmsgs

     文件        307  2018-10-10 15:10  RAM_Test\fuseRelaunch.cmd

     文件        238  2018-10-09 16:33  RAM_Test\ipcore_dir\coregen.cgp

     文件       2453  2018-10-09 16:33  RAM_Test\ipcore_dir\coregen.log

     文件       1277  2018-10-09 16:08  RAM_Test\ipcore_dir\create_ram_ip.tcl

     文件       7721  2013-10-14 02:11  RAM_Test\ipcore_dir\ram_ip\blk_mem_gen_v7_3_readme.txt

     文件       8311  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\doc\blk_mem_gen_v7_3_vinfo.html

     文件    7207569  2013-10-14 02:11  RAM_Test\ipcore_dir\ram_ip\doc\pg058-blk-mem-gen.pdf

     文件       2777  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\example_design\ram_ip_exdes.ucf

     文件       5139  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\example_design\ram_ip_exdes.vhd

     文件       2720  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\example_design\ram_ip_exdes.xdc

     文件      10522  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\example_design\ram_ip_prod.vhd

     文件       1044  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\implement\implement.bat

     文件       1027  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\implement\implement.sh

     文件       2683  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\implement\planAhead_ise.bat

     文件       2578  2018-10-09 16:33  RAM_Test\ipcore_dir\ram_ip\implement\planAhead_ise.sh

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