计算机组成与设计project2

This project is intended to help you to understand the cache architecture and its mechanism. In this project, you will design a first-level data cache controller with Verilog HDL step by step. You may need to review the knowledge about the language to make sure you can finish the project smoothly.

 属性            大小     日期    时间   名称
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     文件     271550  2018-12-13 14:04  project2\2018-project2.pdf

     文件     213392  2018-12-05 23:37  project2\TMS320C621x（C671x）_Two_Level_Internal_Memory_Reference_Guide.pdf

     目录          0  2018-12-06 00:14  project2

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