三星 KLM8G1GEME-B041 datasheet

三星 flash KLM8G1GEME-B041(eMMC5.1+1ynm+based+e_MMC) 数据手册
datasheet e MMC Table of contents 1.0 PRODUCT L|ST… 2.0 KEY FEATURES 3 0 PACKAGE CONFIGURATIONS 3.1 153 Ball Pin configuration 3.1.1 11.5mm x 13mm x 0.8mm Package Dimension 3.2 Product architecture 4.0HS400 mode 5.0 New eMMC5 1 Features 5.1 Overview 445567899999 2 Command Queuing 5.2.1 CMD Set Description 5.2.2 New Response: QsR(Queue Status Register) 5.2.3 Send status. CMD13 5.2.4 Mechanism of CMD Queue operation 525 CMD Queue Register description…… 5.3 Enhanced strobe mode 10 4 RPMB Throughput improve 5.5 Secure Write Protection 11 6.0 Technical notes 6. 1 S/ Algorithm 6.1.1 Partition Management 6.1.1.1 Boot area partition and rpmb area partition 6.1.1.2 Enhanced Partition(Area) 22223 6.1.2 Boot operation 6.1.3 User Density...... 14 6.1.4 Auto Power Saving Mode 14 6.1.5 Performance ,,, 70 REGISTER VALUE 7.1 OCR Register… 7.2 CID Register 16 7.2.1 Product name table(In CID Register). 7.3 CSD Register… 7. 4 Extended CSD Register 18 8.0 AC PARAMETER 1 Timing parameter ““ 8.2 Previous Bus Timing Parameters for DDR52 and Hs200 mode are defined by JEDEC standard 23 8. 3 Bus Timing Specification in H$400 mode 8.3.1 HS400 Device Input Timing 8.3.2 HS400 Device Output Timing 24 8. 4 Bus signal levels 8. 4. 1 Open-drain mode bus signal level 8.4.2 Push-pull mode bus signal level eMM 25 9.0 DC PARAMETER 9. 1 Active Power Consumption during operation 26 2 Standby Power Consumption in auto power saving mode and standby state 9. 3 Sleep Power Consumption in Sleep State 9. 4 Bus Signal Line Load 27 SAMSUNG SAMSUNG ELECTRONICS datasheet e MMC ple read and write to memory using MMC protocol v5. 1 which is a industry standa"' eMMC operation is identical to a mMc device and therefore is a sim- SAMSUNG eMMC is an embedded mmc solution designed in a bGa package form eMMC consists of NAND flash and a MMc controller 3V supply voltage is required for the NAND area (VDDF or VCC)whereas 1. 8V or 3V dual supply voltage (VDD or vccQ)is supported for the MMC controller. SAMSUNG eMMC supports 200MHZ DDR-up to 400MBps with bus widths of 8 bit in order to improve sequential bandwidth, especially sequential read performance There are several advantages of using eMMC. It is easy to use as the Mmc interface allows easy integration with any microprocessor with MMc host Any revision or amendment of NANd is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to faster product development as well as faster times to market The embedded flash management software or FTL(Flash Transition Layer)of eMMC manages Wear Leveling, Bad Block Management and ECC. The FTL supports all features of the Samsung NAND flash and achieves optimal performance 1.0 PRODUCT LIST [Table 1] Product List Interface power ∨DD(1.70V-1.95or 8 GB KLM8G1GEME-B04164Gb MLCx1 91.02% 27-3.6V) 11.5mm x 13mm x 0.8mm153FBGA VDDF(2.7V -36V) 20 KEY FEATURES embedded MultiMediacard Ver. 5.1 compatible SAMSUNG eMMC supports features of eMMC5 1 which are defined in JEDEC Standard Supported Features: Packed command, Cache, Discard, Sanitize, Power Off Notification, Data Tag, Partition types, Context ID, Real Time Clock, Dynamic Device Capacity, Command Queuing, Enhanced Strobe Mode, Secure Write Protection, HS200, HS400, Field Firmware Update Non-supported Features: Large sector Size(4KB) Full backward compatibility with previous MultiMediacard system specification (1bit data bus, multi-eMMC systems) Data bus width: 1bit(Default), 4bit and 8bit MMC I/F Clock Frequency: 0-200MHz MMC IF Boot Frequency 0- 52MHZ Temperature: Operation (-25C -85C), Storage without operation(-40C-85'C) Power: Interface power >VDD(VCCQ)(1.70V -1.95V or 2.7V-36V), Memory power >VDDF(VCC)(2.7V- 3.6V) SAMSUNG datasheet e MMC 3.0 PACKAGE CONFIGURATIONS 3.1 153 Ball Pin Configuration [Table 2 153 Ball Information -Nc DATO A4 DAT 1 DAT2 画画 DAT B3 DATa B4 DAT5 B5 DAT 234567 91011121314 DAT A○的的○○○○○○ K5 RSTN B○如○○O○○○○○ VDD C○@(@○@○○○○○○○ M4 VDD D○○○○ VDD VDD E○○○@③姆的○○① P5 VDD E6 VDDF G F5 VDDE ⊙○○○ J10 VDDF VDDF K○○○网四@姆○○○ VDDI ○○○ M5 CMD M○○○@@○○○○○○○ H5 Data strobe N○c○@四○①○○○○○O J5 SS P○○@③c②○○○@○○○ A6 VSS 回國國 C4 VSS 5 SS H10 VSS N2 VSS N5 VSS P4 VSS P6 SS CLK: Clock input Data Strobe: Newly assigned pin for HS400 mode. Data Strobe is generated from e. MMc to host In HS400 mode, read data and crc response are synchronized with data strobe CMD: a bidirectional signal used for device initialization and command transfers Command operates in two modes, open -drain for initialization and push-pull for fast command transfer DATO-7: Bidirectional data channels. It operates in push-pull mode RST_ n: H/ reset signal pin VDDF (VCC): Supply voltage for flash memory VDD(VCCQ): Supply voltage for memory controller . VDDi: Internal power node to stabilize regulator output to controller core logics VSs: Ground connections 5 SAMSUNG datasheet e MMC 3.1.1 11.5mm x 13mm x 0.8mm Package Dimension #A1 INDEX MARK 11.500.10 1150C.10 0.08 MAX 050×13=6.50 14131211109876543 (Datum A) A eooodooloooooo (Datum B)c ○oo 8 ○OOO OOO⊕ OoO OOO O 9⊙o M OOOOOO申OOOO 153-20300.0 50 20.20Al 0.220.05 6 SAMSUNG datasheet e MMC 3.2 Product Architecture eMMC consists of NAND Flash and Controller. Vop (cco) is for Controller power and VDD(Vcc)is for flash power RESET Core Regulator当 -a2 Roquirod fp 3. v VDD) Control Signal Memory VDDi Data strobe Logic Data bus CMD Block 1.70 195 Voltage 2 2.7 3.6 Vop cap value 2 uF DDF cap. Value DDF 2 F Vppi cap. Value 4.7 UF SAMSUNG datasheet e MMC 4.0HS400 mode eMMC50 product supports high speed DDR interface timing mode up to 400MB/s at 200MHz with 1.8V 1/O supply HS400 mode supports the following features DDR Data sampling method CLK frequency up to 200MHz DDR-up to 400Mbp Only 8-bits bus width available Signaling levels of 1.8V Six selectable Drive Strength(refer to the table below) [Table 3]10 driver strength types Default 50g x1 Default Driver Type Supports up to 200MHz operation Optional 339 1.5 Supports up to 200MHz Operation Optional 66Q x0.75 The weakest driver that supports up to 200MHz operation 3 Optional 100 x0.5 For low noise and low EMI systems Maximal operating frequency is decided by host design. Optional 409 1.2 Supports up to 200MHz DDR operation NOTE: 1)Support of Driver Type- is default for HS200& H$400 Device, while supporting Driver types 1-4 are optional for HS200 HS400 Device [Table 4]Device type values(EXT CSD register: DEVICE TYPE [196]) HS400 Dual Data Rate eMMC 200 MHz-12V 1/O Not support 76543210 HS400 Dual Data Rate eMMC 200 MHz -18V I/O Support HS200 Single Data Rate @200MHz-1.2Vo Not support HS200 Single Data Rate @200MHz-1.8Vo Support High-Speed Dual Data Rate 52MHzZ-12V I/O Not support High-Speed Dual Data Rate @52MHz-1.8。r3Vo Support High-Speed 52MHz-at rated device voltage(s) Support High-Speed 26MHz-at rated device voltage(s) Support [Table 5] Extended CSD revisions(EXT- CSD register: EXT_ CSD_REV[192]) 255-8 Reserved Revision 1.8(for MMC V5. 1) 0x08 8_765432 Revision 1.7(for MMCV5.0) Revision 1.6(for MMC V4.5,V4.51) Revision 1.5(for MMC V4. 41) Revision14(○ bolete) Revision 1.3 (for MMC V4. 3) Revision 1.2 (for MMC V4.2) Revision 1.1(for MMC V4. 1) Revision 1.0(for MMC V4.0) [Table 6 High speed timing values(EXI CSD register: HS_ TIMING [185]) 0x0 Selecting backwards compatibility interface timing Support High speed 0x2 HS200 Support 0x3 HS400 Support 8 SAMSUNG datasheet e MMC 5.0 New eMMC5 1 Features 5. 1 Overview Cache Flushing Report Mandatory Background operation control Mandatory Yes Command Queuing Optional Yes Enhanced strobe Optional Yes RPMB Throughput improve Optional Yes Secure Write Protection Optional Yes 5.2 Command Queuing To facilitate command queuing in eMMC, the device manages an internal task queue that the host can queue during data transfer tasks Every task is issued by the host and initially queued as pending. The device works to prepare pending tasks for execution. When a task is ready far exe cution, its state changes to "ready for execution The host tracks the state of all queued tasks and may order the execution of any task, marked as"ready for execution, by sending a command indicating ts task ID. The device executes the data transfer transaction after receiving the execute command(CMD46/CMD47 5.2.1 CMD Set Description [Table 7] CMD Set Description and Details [31] Reliable Write Request [30] DAT DIR-""write/"1read 29]tag request CMD44 ac/R1/[28: 25] context ID QUEUED TASK PARAMS Define direction of operation(Read or Write)and [24]forced programming Set high priority cmd Queue with task ID [23] Priority: 0"simple /1"high [20: 16]TASK ID [15: 0] number of blocks CMD45 ac/R1[31: 0] Start block address QUEUED TASK ADDRESS Indicate data address for Queued CMD CMD46 adtc/R1[20: 16]TASK ID EXECUTE READ TASK (Read) Transmit the requested number of data blocks CMD47 adtc/R1[20: 16] TASK ID EⅩ ECUTE WRITE TASK (Write)Transmit the requested number of data blocks CMD48 ac/R1b [20: 16] ID Reset a specific task or entire queue [3: 0 ]TM op-code CMDQ TASK MGMT 20: 16] when TM op-code 2h these bits represent TaskID When TM op-code 1h these bits are reserved 5.2.2 New Response: QSR (Queue Status Register) The 32-bit Queue Status Register(QSR) carries the state of tasks in the queue at a specific point in time. The host has read access to this register through device response to SEND_ STATUS command(CMD13 with bit[ 15]=1), R1s argument will be the 32-bit Queue Status Register(QSR). Every bit in the QSR represents the task who's id corresponds to the bit index. If bit QSR[]=0, then the queued task with a Task ID i is not ready for execution. The task may be queued and pending or the Task ID is unused. If bit QSRO= 1, then the queued task with Task Id i is ready for execution 5.2.3 Send status: CMD13 CMD1 3 for reading the Queue Status Register(QSR) by the host. If bit[15] in CMD13's argument is set to 1, then the device shall send an R1 Response with the QSr instead of the Device Status. There is still legacy CMD13 with Response 9 SAMSUNG datasheet e MMC 5.2. 4 Mechanism of CMd Queue operation Host issues CMD44 with Task ID number, Sector, Count, Direction, Priority to the device followed by CMD45 and host checks the Queue Status check with CMD13[15]bits to 1. After that host issues CMD46 for Read or CMD47 for write During CMD queue operation, CMD44/CMD45 is able to be issued at anytime when the Cmd line is not in use 46‖R1 44R145R144R145R 13QSR 44R145‖R1 13QSR *Write Execution Data Data 5.2.5 CMD Queue Register description Configuration and capability structures shall be added to the EXT CSD register, as described below [Table 8] CMD Queuing Support(EXT CSD register: CMDQ SUPPORT [308D Reserved CMD Queue supportability This field indicates whether the device supports command queuing or not OXO: CMD Queue function is not supported Ox1: CMD Queue function is supported [Table 9] Command Queue Mode Enable(EXT CSD register: CMDQ_ MODE_ EN [15]) Reserved This field is used by the host enable command queuing OxO: Queue function is not enabled Ox1: Queue function is enabled [Table 10] CMD Queuing Depth(EXT CSD register: CMDQ DEPTH [307) Reserved N This field is used to calculate the depth of the queue supported by the device Bit encoding [7: 5]: Reserved 4: 0]: N, a parameter used to calculate the Queue Depth of task queue in the device Queue Depth =N+1 5.3 Enhanced strobe mode This product supports Enhanced Strobe in HS400 mode and refer to the details as described in eMMC5. 1 JEDEC standard 5.4 RPMB Throughput improve [Table 11] Related parameter register in EXT CSD: WR REL PARAM [166] Enhanced rPmb reliable write EN RPMB REL WR 4 R Bit[4]: EN RPMB REL WR(R) 0X0: RPMB transfer size is either 256B (single 512B frame)or 512B (Two 512B frame 0 x1: RPMB transfer size is either 256B (single 512B frame ) 512B(Two 512B frame), or 8KB(Thirthy two 512B frames) SAMSUNG