二维dct源代码

Zip file contains Verilog files (*.v) dct.v test_dct.v Vhdl file (*.vhd) dct.vhd The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i. The multiplier instantiation in the verilog files are used when targeting Virtex 2. For all other devices, the instantiations are commented out and the behavioral multiplier code is used. Test_dct contains the test bench which uses the input values as given in the reference "Image and Video Compression Standards" by V. Bhaskaran and K. Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v and idct.v files. The lower level vhdl files are dct.vhd and idct.vhd

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----
     目录           0  2018-09-19 17:48  v文件\
     文件        1373  2018-09-19 16:34  v文件\ALU_tb.v
     文件        1067  2018-09-19 17:46  v文件\approximate_adder16b.v
     文件        1297  2018-09-19 16:55  v文件\bit4ALU.v
     文件        1150  2018-09-19 16:53  v文件\bit8ALU.v
     文件         209  2018-08-10 20:52  v文件\carry_x1.v
     文件        6733  2018-09-19 17:45  v文件\DCT.v
     文件        1714  2018-09-19 16:34  v文件\DCT2D.v
     文件        1488  2018-09-19 16:34  v文件\DCT2D_tb.v
     文件        1643  2018-09-19 16:34  v文件\DCT_tb.v
     文件         930  2018-09-19 16:34  v文件\FE.v
     文件         283  2018-08-10 20:28  v文件\full_adder.v
     文件        1181  2018-09-19 16:34  v文件\RAM.v
     文件        2038  2018-09-19 16:34  v文件\RAMctler.v
     文件        1270  2018-09-19 16:34  v文件\Ram_tb.v
     文件         630  2018-08-10 20:34  v文件\ripple_adder4b.v
     文件        1370  2018-09-19 16:34  v文件\SP.v
     文件        1686  2018-09-19 16:34  v文件\SP_tb.v