• 大小: 166KB
    文件类型: .rar
    金币: 1
    下载: 0 次
    发布日期: 2021-05-14
  • 语言: 其他
  • 标签: verilog  MIPS  CPU  modelsim  

资源简介

verilog编程实现了MIPSCPU的多周期实现。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。

资源截图

代码片段和文件信息

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----

     文件      38060  2013-12-28 00:11  12061115_周其林.docx

     文件       1495  2013-12-27 11:43  Project6(finish)\alu.v

     文件        747  2013-12-27 22:00  Project6(finish)\be_load.v

     文件        496  2013-12-27 22:02  Project6(finish)\be_save.v

     文件       1190  2013-12-22 11:39  Project6(finish)\code.txt

     文件       5539  2013-12-27 23:06  Project6(finish)\controller.v

     文件       2180  2013-12-27 12:26  Project6(finish)\dm.v

     文件        202  2013-12-27 20:29  Project6(finish)\ext.v

     文件        614  2013-12-27 12:06  Project6(finish)\gpr.v

     文件       2456  2013-12-27 12:07  Project6(finish)\head_mips.v

     文件        422  2013-12-27 12:31  Project6(finish)\im.v

     文件       3158  2013-12-28 00:12  Project6(finish)\mips.cr.mti

     文件      86161  2013-12-28 00:12  Project6(finish)\mips.mpf

     文件       1611  2013-12-27 22:58  Project6(finish)\mips.v

     文件        581  2013-12-27 12:01  Project6(finish)\mux.v

     文件        825  2013-12-27 11:49  Project6(finish)\npc.v

     文件        350  2013-12-27 22:02  Project6(finish)\pc.v

     文件        197  2013-12-27 11:36  Project6(finish)\testbench.v

     文件      98304  2013-12-27 23:11  Project6(finish)\vsim.wlf

     文件    2051118  2013-12-27 13:09  Project6(finish)\wave1.bmp

     文件    2051118  2013-12-27 13:10  Project6(finish)\wave2.bmp

     文件      48464  2013-12-27 23:09  Project6(finish)\work\alu\verilog.asm64

     文件       1024  2013-12-27 23:09  Project6(finish)\work\alu\verilog.rw64

     文件       1588  2013-12-27 23:08  Project6(finish)\work\alu\_primary.dat

     文件       2734  2013-12-27 23:08  Project6(finish)\work\alu\_primary.dbs

     文件        802  2013-12-27 23:09  Project6(finish)\work\alu\_primary.vhd

     文件      24816  2013-12-27 23:09  Project6(finish)\work\be_load\verilog.asm64

     文件        400  2013-12-27 23:09  Project6(finish)\work\be_load\verilog.rw64

     文件       1082  2013-12-27 23:08  Project6(finish)\work\be_load\_primary.dat

     文件       1131  2013-12-27 23:08  Project6(finish)\work\be_load\_primary.dbs

............此处省略89个文件信息

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