Verilog实现16位计数器

Verilog实现16位计数器(自增\自减\增减三种模式)

 属性            大小     日期    时间   名称
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     文件        505  2018-12-29 15:16  counter\sim\counter.cr.mti

     文件         48  2018-12-29 14:16  counter\sim\counter.f

     文件      85851  2018-12-29 15:16  counter\sim\counter.mpf

     文件      27116  2018-12-29 15:18  counter\sim\novas.rc

     文件        434  2018-12-29 14:51  counter\sim\run.bat

     文件        430  2018-12-29 14:22  counter\sim\run.bat.bak

     文件         63  2018-12-29 14:18  counter\sim\sim.do

     文件       1243  2018-12-29 15:02  counter\src\rtl\counter.v

     文件        599  2018-12-29 15:13  counter\src\tb\counter_tb.v

     文件        598  2018-12-29 15:04  counter\src\tb\counter_tb.v.bak

     目录          0  2018-12-29 14:08  counter\src\bfm

     目录          0  2018-12-29 15:05  counter\src\rtl

     目录          0  2018-12-29 15:13  counter\src\tb

     目录          0  2018-12-29 14:09  counter\doc

     目录          0  2018-12-29 15:18  counter\sim

     目录          0  2018-12-29 14:08  counter\src

     目录          0  2018-12-29 14:51  counter

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