Verilog实现单周期十条指令的cpu

课程设计所得单周期十条指令cpu，源代码在压缩包里，可略作参考，如果怎么跑都不会就。。。

 属性            大小     日期    时间   名称
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     文件        305  2019-06-22 17:41  ch1\acc.v

     文件        407  2019-06-22 13:36  ch1\ALU.v

     文件       2304  2019-06-23 00:25  ch1\ch1.cr.mti

     文件      97813  2019-06-23 00:25  ch1\ch1.mpf

     文件        936  2019-06-22 23:06  ch1\cpu.v

     文件        199  2019-06-22 23:09  ch1\cputest.v

     文件        847  2019-06-22 22:48  ch1\cu.v

     文件        300  2019-06-22 18:40  ch1\Datastorage.v

     文件        751  2019-06-23 00:24  ch1\ins.v

     文件        751  2019-06-23 00:11  ch1\ins.v.bak

     文件        404  2019-06-22 22:03  ch1\pc.v

     文件        385  2019-06-22 19:19  ch1\register.v

     文件      73728  2019-06-23 00:25  ch1\vsim.wlf

     文件      49152  2019-06-23 00:24  ch1\work\@_opt\_lib.qdb

     文件      32768  2019-06-23 00:24  ch1\work\@_opt\_lib1_0.qdb

     文件          0  2019-06-23 00:23  ch1\work\@_opt\_lib1_0.qpg

     文件      22502  2019-06-23 00:24  ch1\work\@_opt\_lib1_0.qtl

     文件      32768  2019-06-23 00:24  ch1\work\@_opt\_lib2_0.qdb

     文件          0  2019-06-23 00:23  ch1\work\@_opt\_lib2_0.qpg

     文件      10575  2019-06-23 00:24  ch1\work\@_opt\_lib2_0.qtl

     文件      32768  2019-06-23 00:24  ch1\work\@_opt\_lib3_0.qdb

     文件          0  2019-06-23 00:23  ch1\work\@_opt\_lib3_0.qpg

     文件       8440  2019-06-23 00:24  ch1\work\@_opt\_lib3_0.qtl

     文件      32768  2019-06-23 00:24  ch1\work\@_opt\_lib4_0.qdb

     文件      98304  2019-06-23 00:24  ch1\work\@_opt\_lib4_0.qpg

     文件      40235  2019-06-23 00:24  ch1\work\@_opt\_lib4_0.qtl

     文件      32768  2019-06-23 00:24  ch1\work\@_opt\_lib5_0.qdb

     文件       8192  2019-06-23 00:24  ch1\work\@_opt\_lib5_0.qpg

     文件       6332  2019-06-23 00:24  ch1\work\@_opt\_lib5_0.qtl

     文件       3738  2019-06-23 00:24  ch1\work\_info

............此处省略13个文件信息