五级流水线MIPS微处理器部分指令实现Verilog

Verilog实现MIPS处理器部分指令，不乏存在错误，还请指出。

 属性            大小     日期    时间   名称
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     文件        203  2019-01-11 19:03  piplined_processor\ReadMe.txt

     文件      11127  2018-12-24 13:04  piplined_processor\run_vsim\modelsim.ini

     文件         73  2018-12-24 16:10  piplined_processor\run_vsim\run_sim（双击仿真查看仿真结果）.bat

     文件       5151  2018-12-24 16:09  piplined_processor\run_vsim\sim.do

     文件        809  2018-12-24 16:36  piplined_processor\run_vsim\transcript

     文件        118  2018-12-24 16:14  piplined_processor\run_vsim\vlog.args

     文件     114688  2018-12-24 16:37  piplined_processor\run_vsim\vsim.wlf

     文件        282  2018-12-24 16:35  piplined_processor\run_vsim\work\@a@l@u\verilog.prw

     文件       7152  2018-12-24 16:35  piplined_processor\run_vsim\work\@a@l@u\verilog.psm

     文件        874  2018-12-24 16:35  piplined_processor\run_vsim\work\@a@l@u\_primary.dat

     文件        828  2018-12-24 16:35  piplined_processor\run_vsim\work\@a@l@u\_primary.dbs

     文件        376  2018-12-24 16:35  piplined_processor\run_vsim\work\@a@l@u\_primary.vhd

     文件        305  2018-12-24 16:35  piplined_processor\run_vsim\work\@c@p@u_@t@o@p_@t@e@s@t\verilog.prw

     文件       4128  2018-12-24 16:35  piplined_processor\run_vsim\work\@c@p@u_@t@o@p_@t@e@s@t\verilog.psm

     文件        363  2018-12-24 16:35  piplined_processor\run_vsim\work\@c@p@u_@t@o@p_@t@e@s@t\_primary.dat

     文件        508  2018-12-24 16:35  piplined_processor\run_vsim\work\@c@p@u_@t@o@p_@t@e@s@t\_primary.dbs

     文件        254  2018-12-24 16:35  piplined_processor\run_vsim\work\@c@p@u_@t@o@p_@t@e@s@t\_primary.vhd

     文件        543  2018-12-24 16:35  piplined_processor\run_vsim\work\@control@unit\verilog.prw

     文件      18480  2018-12-24 16:35  piplined_processor\run_vsim\work\@control@unit\verilog.psm

     文件       2512  2018-12-24 16:35  piplined_processor\run_vsim\work\@control@unit\_primary.dat

     文件       2370  2018-12-24 16:35  piplined_processor\run_vsim\work\@control@unit\_primary.dbs

     文件        542  2018-12-24 16:35  piplined_processor\run_vsim\work\@control@unit\_primary.vhd

     文件        287  2018-12-24 16:35  piplined_processor\run_vsim\work\data_@memory\verilog.prw

     文件       5768  2018-12-24 16:35  piplined_processor\run_vsim\work\data_@memory\verilog.psm

     文件        495  2018-12-24 16:35  piplined_processor\run_vsim\work\data_@memory\_primary.dat

     文件        654  2018-12-24 16:35  piplined_processor\run_vsim\work\data_@memory\_primary.dbs

     文件        373  2018-12-24 16:35  piplined_processor\run_vsim\work\data_@memory\_primary.vhd

     文件       1090  2018-12-24 16:35  piplined_processor\run_vsim\work\hazard@unit\verilog.prw

     文件      18280  2018-12-24 16:35  piplined_processor\run_vsim\work\hazard@unit\verilog.psm

     文件       1447  2018-12-24 16:35  piplined_processor\run_vsim\work\hazard@unit\_primary.dat

............此处省略48个文件信息