Verilog实现示波器

基于Xilinx vivado工具开发。运行平台：Digilent Basys3开发板，运行tcl文件即可完成工程的综合、布线、bit生成。

 属性            大小     日期    时间   名称
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     文件       1080  2015-02-10 22:11  Oscilloscope\readme.txt

     文件    2192115  2015-02-11 12:05  Oscilloscope\Ready_for_download\B3_OSC_download.bit

     文件       1831  2015-02-10 21:27  Oscilloscope\Src\Constraint\oscilloscope.xdc

     文件      10156  2015-02-09 14:56  Oscilloscope\Src\HDL_source\char_rom_mapping.v

     文件       1874  2015-02-09 19:26  Oscilloscope\Src\HDL_source\clock_control.v

     文件       4796  2015-02-09 12:28  Oscilloscope\Src\HDL_source\Fre_Calculate.v

     文件       5245  2015-02-09 15:38  Oscilloscope\Src\HDL_source\Fre_Vopp_mapping_rom.v

     文件       5619  2015-02-10 21:27  Oscilloscope\Src\HDL_source\OSC_top.v

     文件        875  2015-02-09 13:02  Oscilloscope\Src\HDL_source\trigger.v

     文件       8795  2015-02-09 14:40  Oscilloscope\Src\HDL_source\vga_initials.v

     文件      36140  2015-02-09 15:06  Oscilloscope\Src\HDL_source\waveform_mapping_rom.v

     文件      21964  2015-02-09 12:33  Oscilloscope\Src\HDL_source\waveform_ram.v

     文件      66581  2015-02-09 19:21  Oscilloscope\Src\HDL_source\clock\clock.xci

     文件       4314  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0.dcp

     文件       3035  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0.veo

     文件       3148  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0.xci

     文件      18019  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0.xml

     文件       6254  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0_funcsim.v

     文件       6788  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0_funcsim.vhdl

     文件       1256  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0_stub.v

     文件       1310  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\debounce_0_stub.vhdl

     文件       2713  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\sim\debounce_0.v

     文件        898  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\sim_1\new\debounce_tb.v

     文件       1020  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\sources_1\new\debounce.v

     文件       3004  2015-02-10 21:18  Oscilloscope\Src\HDL_source\debounce_0\synth\debounce_0.v

     文件       3007  2015-02-08 17:36  Oscilloscope\Src\HDL_source\IP_Catalog\XUP_debounce_1.0.zip

     文件       3414  2015-02-07 11:48  Oscilloscope\Src\HDL_source\IP_Catalog\XUP_vga_1.0.zip

     文件       8279  2015-02-09 18:37  Oscilloscope\Src\HDL_source\IP_Catalog\XUP_xadc_1.0.zip

     文件       9758  2015-02-08 17:36  Oscilloscope\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\component.xml

     文件        898  2015-02-08 17:31  Oscilloscope\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sim_1\new\debounce_tb.v

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