SystemVerilog for Verification（最新版）

1 Verifi cation Guidelines ........................................................................... 1 1.1 The Verifi cation Process ................................................................ 2 1.1.1 Testing at Different Levels ............................................... 3 1.1.2 The Verifi cation Plan ........................................................ 4 1.2 The Verifi cation Methodology Manual .......................................... 4 1.3 Basic Testbench Functionality ....................................................... 5 1.4 Directed Testing ............................................................................. 5 1.5 Methodology Basics ...................................................................... 6 1.6 Constrained-Random Stimulus ...................................................... 8 1.7 What Should You Randomize? ...................................................... 9 1.7.1 Device and Environment Confi guration ........................... 9 1.7.2 Input Data ......................................................................... 10 1.7.3 Protocol Exceptions, Errors, and Violations .................... 10 1.7.4 Delays and Synchronization ............................................. 11 1.7.5 Parallel Random Testing .................................................. 11 1.8 Functional Coverage ...................................................................... 12 1.8.1 Feedback from Functional Coverage to Stimulus ............ 12 1.9 Testbench Components .................................................................. 13 1.10 Layered Testbench ......................................................................... 14 1.10.1 A Flat Testbench .............................................................. 14 1.10.2 The Signal and Command Layers .................................... 17 1.10.3 The Functional Layer ....................................................... 17 1.10.4 The Scenario Layer .........................