基于DDS正弦波信号发生器

基于Verilog代码和调用IP核的ROM模块存储波形，实现基于FPGA的正弦波信号输出以及波形的仿真

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     文件       1701  2018-04-03 09:28  SIN\fuse.log

     文件        367  2018-04-03 09:28  SIN\fuse.xmsgs

     文件        252  2018-04-03 09:28  SIN\fuseRelaunch.cmd

     文件       7721  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\blk_mem_gen_v7_3_readme.txt

     文件       8311  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\doc\blk_mem_gen_v7_3_vinfo.html

     文件    7207569  2018-04-03 09:29  SIN\ipcore_dir\blk_mem_gen_v7_3\doc\pg058-blk-mem-gen.pdf

     文件       2684  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.ucf

     文件       4822  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.vhd

     文件       2654  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.xdc

     文件      10398  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_prod.vhd

     目录          0  2018-04-03 09:29  SIN\ipcore_dir\blk_mem_gen_v7_3\doc

     目录          0  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3\example_design

     目录          0  2018-04-03 09:28  SIN\ipcore_dir\blk_mem_gen_v7_3

     目录          0  2018-04-03 09:28  SIN\ipcore_dir

     目录          0  2018-04-03 09:28  SIN

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