WISHBONE接口的UARTVerilog实现

WISHBONE接口的UART（Verilog实现） 内部包含说明文档、源代码、测试平台和工程文件 学习verilong非常好的资料

 属性            大小     日期    时间   名称
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     目录           0  2009-01-22 12:27  RD1042\docs\
     文件      384524  2009-01-22 13:40  RD1042\docs\rd1042.pdf
     文件        7279  2009-01-22 12:24  RD1042\docs\rd1042_readme.txt
     目录           0  2009-01-26 14:24  RD1042\project\
     目录           0  2009-01-26 14:24  RD1042\project\XO\
     文件          92  2009-01-26 14:24  RD1042\project\XO\mico8uart_xo.lpf
     文件         454  2009-01-26 14:24  RD1042\project\XO\mico8uart_xo.syn
     文件         265  2009-01-21 16:11  RD1042\project\XO\uart_tb_tf.udo
     文件         270  2009-01-21 16:06  RD1042\project\XO\uart_tb_tff.udo
     目录           0  2009-01-22 10:37  RD1042\source\
     文件       19089  2009-01-22 09:53  RD1042\source\intface.v
     文件        4498  2009-01-22 09:52  RD1042\source\modem.v
     文件       19331  2009-01-22 09:52  RD1042\source\rxcver.v
     文件        5040  2009-01-13 11:29  RD1042\source\rxcver_fifo.v
     文件          31  2009-01-22 09:48  RD1042\source\system_conf.v
     文件        4045  2009-01-13 13:51  RD1042\source\txcver_fifo.v
     文件       16450  2009-01-22 09:50  RD1042\source\txmitt.v
     文件       11025  2009-01-22 09:51  RD1042\source\uart_core.v
     文件        4510  2009-01-20 13:55  RD1042\source\UART_VhdlWrapper.vhd
     目录           0  2009-01-22 11:37  RD1042\testbench\
     文件         148  2009-01-21 15:46  RD1042\testbench\eval_params.v
     文件        7836  2009-01-12 11:59  RD1042\testbench\Receive_test.v
     文件       11646  2009-01-08 14:16  RD1042\testbench\Transmit_test.v
     文件        7948  2009-01-21 15:53  RD1042\testbench\uart_tb.v
     目录           0  2009-01-22 10:37  RD1042\