基于FPGA用Verilog HDL语言实现的多功能数字钟

这是一个基于FPGA，用Verilog HDL语言实现的多功能数字钟，课程设计的项目。

 属性            大小     日期    时间   名称
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     文件       3989  2017-06-18 22:34  shizhong\shizhong.cache\wt\gui_resources.wdf

     文件        875  2017-06-18 22:34  shizhong\shizhong.cache\wt\java_command_handlers.wdf

     文件        121  2017-06-18 22:26  shizhong\shizhong.cache\wt\project.wpc

     文件       5243  2017-06-18 22:21  shizhong\shizhong.cache\wt\synthesis.wdf

     文件        100  2017-06-18 22:20  shizhong\shizhong.cache\wt\synthesis_details.wdf

     文件       4227  2017-06-18 22:34  shizhong\shizhong.cache\wt\webtalk_pa.xml

     文件        683  2017-06-18 22:34  shizhong\shizhong.hw\hw_1\hw.xml

     文件        343  2017-06-18 22:27  shizhong\shizhong.hw\shizhong.lpr

     文件        421  2017-06-18 22:04  shizhong\shizhong.runs\.jobs\vrs_config_1.xml

     文件        421  2017-06-18 22:19  shizhong\shizhong.runs\.jobs\vrs_config_2.xml

     文件        176  2017-06-18 22:22  shizhong\shizhong.runs\impl_1\.init_design.begin.rst

     文件          0  2017-06-18 22:22  shizhong\shizhong.runs\impl_1\.init_design.end.rst

     文件        176  2017-06-18 22:22  shizhong\shizhong.runs\impl_1\.opt_design.begin.rst

     文件          0  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\.opt_design.end.rst

     文件        176  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\.place_design.begin.rst

     文件          0  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\.place_design.end.rst

     文件        176  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\.route_design.begin.rst

     文件          0  2017-06-18 22:25  shizhong\shizhong.runs\impl_1\.route_design.end.rst

     文件        176  2017-06-18 22:21  shizhong\shizhong.runs\impl_1\.vivado.begin.rst

     文件          0  2017-06-18 22:27  shizhong\shizhong.runs\impl_1\.vivado.end.rst

     文件          0  2017-06-18 22:19  shizhong\shizhong.runs\impl_1\.Vivado_Implementation.queue.rst

     文件        176  2017-06-18 22:25  shizhong\shizhong.runs\impl_1\.write_bitstream.begin.rst

     文件          0  2017-06-18 22:26  shizhong\shizhong.runs\impl_1\.write_bitstream.end.rst

     文件       5587  2017-06-18 22:27  shizhong\shizhong.runs\impl_1\gen_run.xml

     文件        401  2017-06-18 22:19  shizhong\shizhong.runs\impl_1\htr.txt

     文件       1683  2017-06-18 22:22  shizhong\shizhong.runs\impl_1\init_design.pb

     文件       7308  2017-06-18 22:19  shizhong\shizhong.runs\impl_1\ISEWrap.js

     文件       1623  2017-06-18 22:19  shizhong\shizhong.runs\impl_1\ISEWrap.sh

     文件       6598  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\opt_design.pb

     文件      10752  2017-06-18 22:23  shizhong\shizhong.runs\impl_1\place_design.pb

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